1. Field of the Invention
The present invention relates to a circuit to generate periodic signals such as clock signals. More particularly, the present invention relates to a delay locked loop.
2. Art Background
Many high speed electrical systems possess critical timing requirements which dictate the need to generate a periodic clock wave form that possesses a precise time relationship with respect to some reference signal. Conventionally, a phase locked loop (PLL) which employs a voltage control oscillator (VCO) is used to provide the desired clock signal. An example of a PLL is shown in FIG. 1a. However, VCO-based PLLs have some undesirable characteristics. For example, acquisition of the desired timing relationship which requires multiple iterations of signal through the PLL is often slow (typically many hundreds or thousands of clock cycles) because of the time required to drive the VCO to the correct frequency. Furthermore, designing VCOs with ample power supply rejection characteristics is difficult, particularly when implementing circuitry in CMOS, as power supply voltages utilized in such circuitry are designed to be lower and lower to conserve power. An alternative PLL circuit is the delay locked loop (DLL) which generates an output signal a predetermined delay from the input reference signal. A block diagram illustration is shown in FIG. 1b.